Ziatech Corporation ZT 89CT04 Spezifikationen

ZT 8808A/8809AV20 Single Board ComputersOPERATING MANUALFORZT 8808A/8809A REVISION AZT 88CT08A/88CT09A REVISION AMay 1, 19931050 Southwood DriveSan Lu

ContentsPrefetch Pointer (PFP) ... 6-6General Purpose Registers... 6-6Pointers

Application ExamplesSERIAL_8250 RoutineBEGINIndicate to the main program that the interrupt wasreceivedDisable further serial interrupts(no more are d

Application ExamplesProgram Code;;**********************************************************;* *;* PROGRAMMING ABSTRACT *;* *;************************

Application Examples;;***********************************************************;* *;* SYSTEM EQUATES *;* *;*****************************************

Application Examples; REG #1 INTERRUPT ENABLE REG (W)PORT_INTEN EQU 001H ; INTERRUPT EN.PORT_DLAMB EQU 001H ; IF DLAB=1, MSB DIV.ERBI EQU 01H ; EN INT

Application Examples; REG #6 MODEM STATUS REG (R)PORT_MODS EQU 006H ; MODEM STATUSDCTS EQU 01H ; DELTA CTSDDSR EQU 02H ; DELTA DSRTERI EQU 04H ; TRAIL

Application ExamplesTYPE_8 DD ? ; 8259A IR0-TIMER 0TYPE_9 DD ? ; 8259A IR1-KEYBDTYPE_10 DD ? ; 8259A IR2-TIMER2 (W6B)TYPE_11 DD ? ; 8259A IR3-COM2TYPE

Application Examples;***********************************************************;* *;* INTERRUPT HANDLERS *;* *;**************************************

Application Examples;***********************************************************;* *;* PROCEDURES *;* *;**********************************************

Application Examples;LED_STROBE PROC;; THIS PROCEDURE STROBES THE LED ON THE ZT 8809A,; THEREBY INDICATING TO THE USER THE INTERRUPT EXPECTED WAS RECE

Application ExamplesINIT_UART PROC;; THIS PROCEDURE IS CALLED TO INITIALIZE A UART. THE FOL-; LOWING PARAMETERS ARE INITIALIZED:;; 8-BIT CHARACTER LEN

ContentsLine Status Register ... 8-26Interrupt ID Register... 8-28Interrup

Application Examples;***********************************************************;* *;* TEST CODE *;* *;***********************************************

Application Examples;MOV AL,EIRBO ; ENABLE DATA TRANSMIT; INTERRUPTPUT UART1+PORT_INTEN ; AT THE UART INTERRUPT; ENABLE REGSTI ; ENABLE INTERRUPTSMOV

Application ExamplesEXAMPLE 2: POWER-FAIL/WATCHDOG TIMERObjectives• Write routines for system initialization and system restart afterpower-fail.• Writ

Application ExamplesSystem RequirementsThe following example assumes a ZT 8809A configured with thefactory default jumper assignments, with the follow

Application ExamplesThe following application example is written with both methods ofpower-fail detection in mind. The flowchart indicates that twodif

Application ExamplesSoftware OutlineMAIN ProgramBEGINPoint to battery-backed RAM(segment location DC00h for STD DOS)If "System Data Saved" f

Application ExamplesINIT RoutineBEGINInitialize the NMI routine pointerInitialize the segment registersInitialize the software dataInitialize the hard

Application ExamplesIf yes, halt the system, awaiting system batteryreplacement (for systems powered by battery only)If no, read SLIN* (bit 3) at the

Application ExamplesFlowcharts For AC Power-Fail & Watchdog InterruptsMAIN PROGRAMSTARTSET ES = BATTERY BACKED RAM(DC00h IS STD DOS DEFAULT)SYSTEM

Application ExamplesRESET ROUTINESTARTRETURNINITIALIZE THE NMIINTERRUPT POINTERRESTORE CRITICALPROGRAM DATARESTORE PROGRAMSEGMENT REGISTERSTRIGGER THE

ContentsChapter 12. INTERRUPT CONTROLLER (8259A) 12-1OVERVIEW... 12-3I/O PORT ADDRESSES...

Application ExamplesINIT ROUTINESTARTRETURNINITIALIZE THE NMIINTERRUPT POINTERINITIALIZE THESEGMENT REGISTERSINITIALIZE THESOFTWARE DATATRIGGER THEWAT

Application ExamplesNON-MASKABLE INTERRUPTSERVICE ROUTINE STARTTRIGGER THEWATCHDOG TIMERIS IT SET?YESOTHER NMI SO CHECKFOR SOURCES ELSE-WHERE IN THE S

Application ExamplesAC POWER FAILDETECTEDIS POWERFAIL CIRCUITUSED TO DETECTLOW BATTERY SUPPLYVOLTAGE TOSYSTEM?YESHALT PROCESSOR TOAWAIT MAINBATTERY SU

Application ExamplesCALL RESET ROUTINENOENDRETURN FROMINTERRUPTREINITIALIZE THE INTER-RUPT CONTROLLER TOCLEAR IRRTHE POWER FAILCONDITION IS ENDEDIT MU

Application ExamplesEXAMPLE 3: REAL-TIME CLOCK DRIVERSObjectives• Write the read and write routines which can initialize the timeand read it back.• Wr

Application ExamplesENDWRIT_CLK RoutineBEGINWrite 64 bytes of data into the real-time clockRead the real-time clock once to reset the comparisonregist

Chapter 5MEMORY AND I/O CAPABILITYContents PageOVERVIEW ... 5-1MEMORY ADDRESSING...

Memory and I/O CapabilityMEMORY ADDRESSINGThe ZT 8809A processor board is capable of addressing up to1 Mbyte of memory, both on-board and to the STD b

Memory and I/O CapabilityAlso included on-board is a 32 Kbyte static RAM, referred to as theH: drive in STD DOS systems prior to BIOS Version 3.0 and

Memory and I/O CapabilityMEMORY MAPSFigures 5-1 through 5-6 represent some of the possible memory mapsfor the ZT 8809A, along with jumper configuratio

ContentsIV. APPENDICESAppendix A. JUMPER CONFIGURATIONS A-1OVERVIEW... A-1JUMPER DESCRIPTIONS...

Memory and I/O CapabilityZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39

Memory and I/O CapabilityFigures 5-3 and 5-4 also show an STD DOS system, with one256 Kbyte EPROM drive and 640 Kbytes of system RAM.FFFFFhD8000hA0000

Memory and I/O CapabilityZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39

Memory and I/O CapabilityFigures 5-5 and 5-6 show the factory default configuration for non-DOS systems. Two of the sockets are configured to accept 6

Memory and I/O CapabilityZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39

Memory and I/O CapabilityBATTERY BACKUPAll on-board RAM may be battery-backed by a 3.9 V, 1 Amp-hourlithium battery installed on the ZT 8809A. The 32

Memory and I/O CapabilityMEMORY DEVICE LOCATIONSFigure 5-7 shows the physical locations of the RAM and EPROMsockets on the ZT 8809A. Location 5D1 is t

Memory and I/O CapabilitySockets 3D1 and 5D1Sockets 3D1 and 5D1 as well as the battery-backed RAM arecontrolled primarily by jumpers W57-59. The eight

Memory and I/O CapabilitySockets 7D1 and 9D1Sockets 7D1 and 9D1 are controlled primarily by jumpers W55 andW56. Table 5-2 shows the three possible mem

Memory and I/O CapabilityDEVICE ACCESS TIMESTable 5-3 shows the maximum chip select access times allowed by theZT 8808A and ZT 8809A for on-board RAM

TABLESTable 3–1 Processor Speed Comparison. ... 3-3Table 3–2 Serial Communications Standards... 3-7Table 5–1 M

Memory and I/O CapabilityINPUT/OUTPUT ADDRESSINGThe I/O addressability of the ZT 8809A is 64 Kbytes, equal to that ofthe V20 and 8088 series microproc

Memory and I/O CapabilityI/O Expansion (IOEXP) provides an additional address line for STDbus I/O boards, and may be jumpered to Vcc or ground via jum

Chapter 6CPU DESCRIPTION (V20)Contents PageV20 OVERVIEW ... 6-2Segment Registers...

CPU DescriptionV20 OVERVIEWThe microprocessor on board the ZT 8809A is an NEC V20, which isan 8088 compatible microprocessor with a 16-bit internal an

CPU DescriptionEach unit contains several registers important to the programmer. Inthe following description of these registers, the designator in bra

CPU DescriptionAll memory addresses are specified by a segment and an offset. The16-bit segment is shifted four binary digits to the left and added to

CPU DescriptionProgram variables generally reside in the data segment, referenced bythe data segment 0 register (DS0) [DS]. The offset of each variabl

CPU DescriptionPrefetch Pointer (PFP)This is a 16-bit binary counter. It contains the segment offset used tocalculate a program memory address. The Bu

CPU DescriptionPointers and Index RegistersThese 16-bit registers serve as base pointers and index registers whenaccessing the memory using the based

CPU DescriptionProgram Status Word (PSW) [FL]The program status word is a 16-bit register containing status andcontrol flag information important to C

TablesTable B–9 J5 Pin Assignments. ... B-17Table B–10 J6 Pin Assignments... B-18Table B–11

CPU DescriptionV20 ARCHITECTURAL ENHANCEMENTSThis section focuses on the architectural enhancements that the V20provides which improve its speed over

CPU Description16/32-Bit Temporary Shift Registers (TA,TB)Two 16-bit shift registers have been added for use by multiplicationand division instruction

CPU DescriptionEnhanced and Unique InstructionsThe V20 implements all of the 8088/8086 instructions. It also has alist of enhanced instructions as wel

CPU DescriptionMODE OPERATIONS - 8080 EMULATION MODEDesigns based on 8080 and 8085 microprocessors have two majorlimitations: not enough performance a

CPU DescriptionFigure 6-2 illustrates the possible modes of operation for the V20processor and the methods used to transfer between them.HOLD REQ / HO

CPU DescriptionBreak for Emulation (BRKEM)This is the basic instruction used to start the 8080 emulation mode.This instruction operates identically to

CPU DescriptionCall Native Routine (CALLN)The CALLN instruction makes it possible to call native modesubroutines when in emulation mode. The processin

CPU DescriptionRegister Use in Emulation ModeRegister names for the 8080 processor differ from those of the V20.The V20 registers must therefore consi

CPU DescriptionKeep in mind that the use of independent stack pointers in emulationmode allows independent stack areas to be secured for each mode,whi

CPU DescriptionDMA SUPPORTThe STD-80 Series Bus Specification defines two signals used byprocessor boards and DMA devices to exchange control of the S

ILLUSTRATIONSFigure 1–1 ZT 8809A Functional Block Diagram. ... 1-5Figure 2–1 Non-DOS Factory Default Jumper Configuration... 2-8Fig

CPU DescriptionFigure 6-3 illustrates the signals required for a transfer between anSTD bus DMA controller and the ZT 8809A.A0-A19D0-D7BUSRQ*BUSAK*RD*

CPU DescriptionRESET STATEThe ZT 8809A contains on-board power-fail detection logic thatdetects DC, and optionally AC, power failure. This topic is co

CPU DescriptionWAIT-STATE GENERATORThe ZT 8809A contains a one wait-state generator for use with slowermemory and I/O boards, to allow for an increase

Chapter 7NUMERIC DATA PROCESSOR (8087)Contents PageOVERVIEW ... 7-1ZSBC 337 PIGGYBACK PROCESSOR...

Numeric Data Processor (8087)The 8087 offers numeric data formats and arithmetic operations thatconform to the IEEE Microprocessor Floating Point Stan

Numeric Data Processor (8087)zSBC 337 PIGGYBACK PROCESSORThe large number of memory sockets on the ZT 8809A necessitatesthe use of Ziatech’s zSBC pigg

Numeric Data Processor (8087)WARNING!The following procedure must be done at a static-freeworkstation to avoid damage to the V20 or 8087components.INS

Numeric Data Processor (8087)5. For added mechanical support of the zSBC 337 module, anoptional spacer may be added between the module and theZT 8809A

Numeric Data Processor (8087)6. Refer to Figure 7-1 for an illustration of the zSBC 337installation.Note: If you install a hybrid version of the 128 K

Numeric Data Processor (8087)COPROCESSOR INTERFACECommunication between the 8087 and the V20 occurs over therequest/grant, queue-status, and busy line

IllustrationsFigure 11–3 Control Word Format. ... 11-7Figure 11–4 Counter Latch Command Format... 11-9Fig

Numeric Data Processor (8087)The 8087’s busy signal informs the V20 that the 8087 is executing aninstruction. It is connected to the V20 POLL/[8088 TE

Numeric Data Processor (8087)INTERRUPT/NUMERIC ERRORSTwo courses of action are possible when a numeric error occurs: TheNDP can handle the error itsel

Numeric Data Processor (8087)Some very simple applications may mask all of the numeric errors. Inthis simple case, the 8087 interrupt request (INT) si

Numeric Data Processor (8087)No 8087 interruptsAll errors on the 8087 are always masked. Numeric interrupts are notpossible. Leave the 8087 INT signal

Numeric Data Processor (8087)Use the lowest priority interrupt input to the interrupt controller forthe 8087, which is IR7 at the PIC. This requires w

Numeric Data Processor (8087)REFERENCES– Cooner, Jerome, "An Implementation Guide to a ProposedStandard for Floating Point,"Computer, Instit

Chapter 8SERIAL COMMUNICATIONS (16C452)Contents PageOVERVIEW ... 8-2SERIAL COMMUNICATIONS PROTOCOL..

Serial Communications (16C452)OVERVIEWThis chapter describes the two 16C450-equivalent serial portsavailable on the ZT 8809A. They are referred to as

Serial Communications (16C452)SERIAL COMMUNICATIONS PROTOCOLThe following paragraphs describe the functioning of a serial data linkbetween the ZT 8809

Serial Communications (16C452)In the transmit loop, CTS is tested until set, indicating that the otherdevice is ready to receive data. CTS occurs when

Chapter 1INTRODUCTIONContents PageOVERVIEW ... 1-1ZT 88CT08A and ZT 88CT09A...

Serial Communications (16C452)Data Communications Equipmnent(DCE)ZT 8808A/8809A COM 2POWER-UPData Terminal Equipment(DTE)OTHERPOWER-UPDo I xmit?†Is C

Serial Communications (16C452)The ZT 8809A COM1 and COM2 are shipped configured as DCE.However, if the opposite configuration is desired for either of

Serial Communications (16C452)W17W18W19W20W21W28W27W26W25W24W23W22W29W31W32W30ZT 8809A REV AJ1BBBAAAWire wrap to loop backRTS to CTS on COM2.Wire wra

Serial Communications (16C452)SERIAL INTERFACE (RS-232-C/422/485)The ZT 8809A provides two high-speed RS-232-C serial ports. Theseuse the same program

Serial Communications (16C452)D7-D0DATABUSBUFFERRECEIVERBUFFERREGISTERINTERNALDATA BUSRECEIVERSHIFTREGISTERSINRECEIVERTIMING &CONTROLLINECONTROLR

Serial Communications (16C452)The ZT 8809A provides fully buffered RS-232-C serial data andcontrol lines via two connectors, supplying the ±12 V swing

Serial Communications (16C452)Signal DefinitionsThe following is a description of each of the 16C452 signal inputs andoutputs in the signal name. The

Serial Communications (16C452)Data-Terminal-Ready (DTR0*, DTR1*)Each DTR* pin can be set active (low) by writing a logical 1 to theDTR bit in the Mode

Serial Communications (16C452)Ring Indicator Inputs (RI0*, RI1*)When active (low), RI* indicates that a telephone ringing signal hasbeen received by t

Serial Communications (16C452)Reset Control (RESET*)The ZT 8809A contains power-up and pushbutton reset circuitry thatdrives the RESET* input signal a

IntroductionA performance increase over 8088-based STD CPU boards isachieved in part by the use of the NEC V20 microprocessor. This isan 8088 compatib

Serial Communications (16C452)Request-To-Send (RTS0*, RTS1*)The RTS* pin is set active (low) by writing a logical 1 to bit 1 of theassociated UART’s M

Serial Communications (16C452)SERIAL REGISTERSThis section describes the individual UART registers.You may access or control any of the serial registe

Serial Communications (16C452)Table 8-2ZT 8809A I/O Port Assignments.I/O Port I/O Address I/O Read Register I/O Write RegisterBase +0 3F8h Data Buffer

Serial Communications (16C452)Table 8-316C452 Addressable Registers Summary.0 DLAB = 0 0 DLAB = 0 1 DLAB = 023Receive Buffer(Read Only)Transmit Buffer

Serial Communications (16C452)Table 8-316C452 Addressable Registers Summary (continued).Register AddressBitNo.0 DLAB = 1 1 DLAB = 1467DivisorLatch (LS

Serial Communications (16C452)Transmit and Receive Buffer RegistersThe Transmitter Buffer register and Receiver Buffer register are dataregisters hold

Serial Communications (16C452)Line Control Register(2FBh, 3FBh; R/W)Use the Line Control register (LCR) to specify the format of theasynchronous data

Serial Communications (16C452)Bit 2 Bit 2 specifies the number of stop bits in thetransmitted or received serial character. If bit 2 is alogical 0, on

Serial Communications (16C452)Bit 6 This is the Set Break Control bit. When bit 6 is alogical 1, the serial output (SOUT) is forced to thespacing (log

Serial Communications (16C452)Baud Rate GeneratorThe serial baud rate generator takes the clock input (1.8432 MHz) anddivides it by any divisor from 1

ZIATECHWARRANTYZiatechHardware:Withintwoyearsofshippingdate,Ziatechwillrepairorreplaceproductswhichprovetobedefectiveinmaterialsand/orworkmanship,prov

IntroductionAll RAM and the real-time clock may be optionally battery-backed bya 1 Amp-hour lithium battery. DC power failure detection is providedto

Serial Communications (16C452)Table 8-4Baud Rate Table.Baud Rates Using 1.8432 MHz Clock (F)Baud Rate Divisor % Error(B) (D)50 2304 -75 1536 -110 1047

Serial Communications (16C452)Line Status Register(2FDh, 3FDh; R/W)This 8-bit register provides status information to the CPU concerningthe data trans

Serial Communications (16C452)Bit 4 This bit is the Break Interrupt (BI) indicator. Bit 4 isset to logical 1 whenever the received data input isheld i

Serial Communications (16C452)Interrupt ID Register(2FAh, 3FAh; R)The Interrupt Identification register (IIR) stores an identification codeor "ID

Serial Communications (16C452)Information stored in the IIR indicates that a prioritized interrupt ispending. The source of the interrupt is also indi

Serial Communications (16C452)Interrupt Enable Register(2F9h, 3F9h; R/W)The Interrupt Enable register (IER) enables the four interrupt sourcesof the s

Serial Communications (16C452)Modem Control Register(2FCh, 3FCh; R/W)The Modem Control register (MCR) controls the interface with themodem or data set

Serial Communications (16C452)Bit 4 This bit provides a loopback feature for diagnostictesting of the 16C452. When bit 4 is set to logical 1, thefollo

Serial Communications (16C452)Modem Status Register(2FEh, 3FEh; R)The Modem Status register (MSR) provides the current state of thecontrol lines from

Serial Communications (16C452)Bit 5 This bit is the complement of the Data-Set-Ready(DSR*) input. When set, this bit indicates that themodem is ready

IntroductionFEATURES OF THE ZT 8809A• STD-80 and STD 32 bus compatible• Optional CMOS versions available• 8088/8086 code compatible• Four 32-pin memor

Chapter 9CENTRONICS PRINTER INTERFACEContents PageOVERVIEW ... 9-1PRINTER PORT OUTPUT CHARACTERISTIC

Centronics Printer InterfaceThe printer interface is a bidirectional parallel data port that fullysupports the parallel Centronics type printer. This

Centronics Printer InterfacePRINTER PORT OUTPUT CHARACTERISTICSThe current drive capabilities of the 16C452 printer port signals aretabulated below in

Centronics Printer InterfaceUSING THE PRINTER PORTPhysical access to the printer port may be gained through connectorJ6, a 20-pin header located behin

Centronics Printer InterfaceREGISTER DEFINITIONS/ADDRESSESPrinter Port registers are accessed at I/O addresses 0378h through037Ah, with 037Bh unused.

Centronics Printer InterfaceData PortThe Data Port register is an 8-bit bidirectional register with an outputcontrol signal LPTOE* at connector J6, pi

Centronics Printer InterfaceStatus PortThe Status Port register has five read-only status bits:1. Busy (BUSY)2. Acknowledge (ACK*)3. Paper Error (PE)4

Centronics Printer InterfaceControl PortThe Control Port register has four input/output signals:1. Select In (SLIN*)2. Initialize (INIT*)3. Autofeed (

Centronics Printer InterfaceInterrupt CapabilitySet IRQ ENB to logical 1 to enable the interrupt from the printer port.Set IRQ ENB to 0 to disable the

Centronics Printer InterfaceShared SignalsFour printer port signals on the ZT 8809A (INIT*, AFD*, ERR*, andSLIN*) are shared by various logic function

Introduction3Counter/TimersInterruptControllerRS-232-CSerialRS-232-C/RS-422/485SerialCentronicsPrinterI/O32K RAM(OptionalBatteryBackup)ClockSlowdownan

Centronics Printer InterfaceSelect In (SLIN*) is used for SLOW/FAST control, to allow thesoftware to dynamically control the processor clock frequency

Centronics Printer InterfaceDISABLING SHARING OF PRINTER PORTSIGNALSThis section describes how to dedicate the shared printer port signalsto printer u

Centronics Printer Interface3. Finally, modify the ZT 90039 printer cable. If you are usingSTD DOS, all four signals (AFD*, ERROR*, INIT*, andSLIN*) m

Centronics Printer InterfaceOPTIONAL PRINTER CABLE PINOUTTable 9-5 below defines the pinout for the ZT 90039 printer portcable, including the frontpla

Centronics Printer InterfacePRINTER PORT RESET STATEThe system reset signal does not affect the printer port inside theVL 16C452. Following a power-up

Chapter 10REAL-TIME CLOCK (DS 1215)Contents PageOVERVIEW ... 10-1OPERATION...

Real-Time Clock (DS 1215)The memory management portion provides the necessary supportcircuitry to prevent an invalid chip access to a RAM when power i

Real-Time Clock (DS 1215)OPERATIONTo access the real-time clock in an STD DOS system, use the DOSfunctions "Time" and "Date" when

Real-Time Clock (DS 1215)Next, the 64-bit signature must be sent to the timekeeper by executing64 consecutive write cycles containing the proper data

Real-Time Clock (DS 1215)TIMECHIP COMPARISON REGISTERDEFINITIONByte 0Byte 1Byte 2Byte 3Byte 4Byte 5Byte 6Byte 776543210C53A5CC53AA35CA311000101000111

IntroductionFUNCTIONAL BLOCKSFigure 1-1 illustrates the ZT 8809A’s functional blocks. A briefdescription of each block follows.V20 (uPD70108) Processo

Real-Time Clock (DS 1215)TIMEKEEPER REGISTER INFORMATIONTimekeeper information is contained in eight registers of 8 bits eachthat are sequentially acc

Real-Time Clock (DS 1215)TIMECHIP REGISTER DEFINITIONRegister01234567765432100.1 SEC 0.01 SEC10 SEC SECONDS10 MINMINUTES0077712/24010A/PHRHOURDAYDATEM

Real-Time Clock (DS 1215)AM/PM 12/24-Hour ModeThe timekeeper is able to return data in a 12- or 24-hour mode,selected by bit 7 of register 3. When hig

Chapter 11COUNTER/TIMERS (8254)Contents PageOVERVIEW ... 11-2BLOCK DIAGRAM...

Counter/Timers (8254)OVERVIEWThree programmable 16-bit counter/timers on the ZT 8809A areimplemented in an Intel 8254 chip. These timers can handle in

Counter/Timers (8254)BLOCK DIAGRAMFigure 11-1 illustrates the block diagram of the 8254. The data busbuffer is a three-state, bidirectional, 8-bit buf

Counter/Timers (8254)COUNTER/TIMER ARCHITECTUREEach counter is fully independent and may operate in a unique mode.Only one counter/timer is described

Counter/Timers (8254)The Status register shown in Figure 11-2, when latched, contains thecurrent contents of the Control Word register and status of t

Counter/Timers (8254)OPERATIONReset StateAfter power-up, the state of the 8254 is undefined. The mode, countvalue, and output of all counter/timers ar

Counter/Timers (8254)If a counter is programmed to read or write two-byte counts, thefollowing precaution applies: a program must not transfer control

IntroductionWait-State GeneratorTo accommodate I/O and memory boards needing more time foraccess, the ZT 8809A contains a one wait-state generator. If

Counter/Timers (8254)Read OperationsIt is possible to read the value of a counter without disturbing thecount in progress. Three possible methods for

Counter/Timers (8254)D7 D6 D5 D4 D3 D2 D1 D0SC1 SC0 0 0 X X X XI/O Address = 43h RD = 1 WR = 0SC1, SC0 - specify counter to be latchedSC1SC0Counter001

Counter/Timers (8254)If a counter is latched and then some time later latched again beforethe count is read, the second Counter Latch command is ignor

Counter/Timers (8254)Read-Back CommandThe third method of reading the 8254 is through use of the Read-Backcommand. This command allows you to check th

Counter/Timers (8254)The counter status format is shown in Figure 11-5. Bits D5 throughD0 contain the counter’s programmed mode exactly as written in

Counter/Timers (8254)NULL COUNT bit D6 indicates when the last count written to theCount register (CR) has been loaded into the Counting Element (CE).

Counter/Timers (8254)If multiple status latch operations of the counter(s) are performedwithout reading the status, all but the first are ignored; the

Counter/Timers (8254)Table 11-1Read-Back Command Example.COMMANDD7 D6 D5 D4 D3 D2 D1 D0DESCRIPTION RESULTS11000010 Read back count and Count and statu

Counter/Timers (8254)Mode DefinitionsThe following modes are defined for use in describing the operationof the 8254.CLK Pulse: A rising edge, then a f

Counter/Timers (8254)If a new count is written to the counter, it will be loaded on the nextCLK pulse and counting continues from the new count. If a

IntroductionJumpers are provided to select whether the following three groups ofdevices, either individually or as a whole, are to be battery-backed:•

Counter/Timers (8254)Mode 2: Rate GeneratorThis mode functions like a divide-by-N counter. It is typically used togenerate a real-time clock interrupt

Counter/Timers (8254)Mode 3: Square Wave ModeMode 3 is typically used for baud rate generation. Mode 3 is similarto Mode 2 except for the duty cycle o

Counter/Timers (8254)Odd counts: OUT is initially high. The initial count minus one(an even number) is loaded on one CLK pulse andthen is decremented

Counter/Timers (8254)This allows the sequence to be "retriggered" by software. OUTstrobes low N + 1 CLK pulses after the new count of N is w

Counter/Timers (8254)Table 11-2Gate Pin Operations Summary.Signal LowStatus or Going Rising HighModes Low0 Disables —— EnablesCounting Counting1 —— 1.

Counter/Timers (8254)Operation Common to All ModesProgrammingWhen a Control Word is written to a counter, all Control Logic isimmediately reset and OU

Counter/Timers (8254)CounterNew counts are loaded and counters are decremented on the fallingedge of CLK.The largest possible initial count is 0. This

Counter/Timers (8254)Counter Use by STD DOS and STD ROMThe use of these counters by STD DOS is limited to the use ofcounter/timer 0 as the DOS Timer 0

Chapter 12INTERRUPT CONTROLLER (8259A)Contents PageOVERVIEW ... 12-3I/O PORT ADDRESSES...

Special Fully Nested Mode ... 12-25Automatic Rotating Mode... 12-26Specific Rotating Mode...

IntroductionReal-Time ClockThe real-time clock on the ZT 8809A is a Dallas SemiconductorDS 1215. It keeps track of hundredths of seconds, seconds, min

Interrupt Controller (8259A)OVERVIEWThe Programmable Interrupt Controller (PIC) is an Intel 8259Adevice (or equivalent). It is capable of monitoring e

Interrupt Controller (8259A)OPERATION OVERVIEWThe basic functions of the PIC are to resolve the priority of interruptrequests, issue a single interrup

Interrupt Controller (8259A)All 256 interrupt types are located in absolute memory locations 0through 3FFh, which make up the V20’s interrupt vector t

Interrupt Controller (8259A)When the V20 receives an interrupt vector byte from the 8259A, itmultiplies its value by four to acquire the address of th

Interrupt Controller (8259A)FUNCTIONAL DESCRIPTIONFigure 12-2 shows a block diagram of the 8259A. The PIC is dividedinto eight major blocks for explan

Interrupt Controller (8259A)Interrupt Request Register (IRR)All interrupt requests are input to the Interrupt Request register (IRR).The 8-bit IRR mai

Interrupt Controller (8259A)Priority Resolver (PR)All interrupt requests are latched into the IRR. Those not masked bythe IMR are input to the Priorit

Interrupt Controller (8259A)Read/Write Control LogicThe Read/Write Control Logic controls command and data transferbetween the PIC and the CPU. This f

Interrupt Controller (8259A)PROGRAMMABLE REGISTERSThe PIC is initialized with the Initialization Control Words 1 through4 (ICW1-4). This must take pla

Interrupt Controller (8259A)Initialization Control Words (ICW1-4)Initialization of the PIC consists of writing from three to four bytes, orInitializat

IntroductionCounter/TimersThe ZT 8809A has three independent 16-bit counter/timers, each ofwhich can be used as a timer or event counter. The clock fr

Interrupt Controller (8259A)D7 D6 D5 D4 D3 D2 D1 D00001LTIM0S1ICW1D7 D6 D5 D4 D3 D2 D1 D0S7 S6 S5 S4 S3 S2 S1 S0D7 D6 D5 D4 D3 D2 D1 D0A15 A14 A13 A12

Interrupt Controller (8259A)ICW2The second Initialization Control Word (ICW2), also required in allmodes of operation, is located at I/O address 21h.

Interrupt Controller (8259A)ICW4The fourth Initialization Control Word (ICW4), required for all modesof operation, is located at I/O address 21h. It c

Interrupt Controller (8259A)ICW SummaryIn summary, three or four ICWs are required to initialize the masterand each slave PIC. Specifically:• Master P

Interrupt Controller (8259A)M7 M6 M5 M4 M3 M2 M1 M0INTERRUPT MASK1 = MASK SET0 = MASK RESETD7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D00 34567120 10

Interrupt Controller (8259A)OCW1OCW1 is used solely for 8259A masking operations. It is located atI/O address 21h. It provides a direct link to the IM

Interrupt Controller (8259A)EOI The EOI bit is used for all End-Of-Interrupt commands(not an automatic End-Of-Interrupt mode). If EOI is setto 1, a fo

Interrupt Controller (8259A)RR The RR bit is used to execute the read registercommand. If RR is set to 1, the read register commandis issued and the s

Interrupt Controller (8259A)8259A I/O PORT ADDRESSESThe 8259A programmable interrupt controller on the ZT 8809A usesI/O port addresses 20h or 21h. I/O

Interrupt Controller (8259A)INTERRUPT ASSIGNMENTS ON THE ZT 8809AThe PIC has eight interrupt inputs, IR0 through IR7. Figure 12-5illustrates the inter

IntroductionInterruptsThe programmable interrupt controller (PIC) on the ZT 8809A is anIntel 8259A-2 or equivalent. It has eight interrupt inputs that

Interrupt Controller (8259A)Jumper SelectionsInterrupt LevelABABABABABABABABW5 IROW4 IR1W6 IR2W7 IR3W8 IR4W2, W9 IR5W3, W10 IR6W11 IR78087 InterruptTi

Interrupt Controller (8259A)OPERATION OF THE INTERRUPT CONTROLLERInterrupt operation of the 8259A falls under three categories:priorities, triggering,

Interrupt Controller (8259A)Special Fully Nested ModeThis mode is used only when one or more PICs are cascaded to theZT 8809A master PIC. In the casca

Interrupt Controller (8259A)Automatic Rotating ModeIn this mode, the interrupt priority rotates. Once an interrupt on agiven input is serviced, that i

Interrupt Controller (8259A)The special mask mode is useful when one or more interrupts aremasked. If for any reason an input is masked while it is be

Interrupt Controller (8259A)Level-Triggered ModeWhen in the level-triggered mode, the 8259A recognizes any active(high) level on an IR input as an int

Interrupt Controller (8259A)Edge-Triggered ModeIn the edge-triggered mode, the 8259A recognizes only interrupts thatare generated by an inactive (low)

Interrupt Controller (8259A)A brief review of the registers’ general descriptions follows.• IRR (Interrupt Request Register): Specifies all interrupts

Interrupt Controller (8259A)EOI COMMANDSUpon completion of an interrupt service routine, the 8259A needs tobe notified so its ISR can be updated. This

Interrupt Controller (8259A)Specific EOI CommandsA specific EOI command sent from the microprocessor lets the8259A know when a service routine of a pa

IntroductionCentronics Printer/General Purpose I/O PortA Centronics printer interface is included on the ZT 8809A. It maydrive a Centronics-compatible

Interrupt Controller (8259A)Special consideration should be given, however, when deciding to usethe automatic EOI mode because it disturbs the fully-n

Interrupt Controller (8259A)RESETThe 8259A does not receive a reset signal upon power-up or whenpushbutton reset is applied to the ZT 8809A. The part

Chapter 13ZT 88CT08A/88CT09A CMOS BOARDSContents PageOVERVIEW ... 13-1FUNCTIONAL DIFFERENCES...

ZT 88CT08A/88CT09A CMOS BoardsFUNCTIONAL DIFFERENCESLogic Family (CT vs. C)There are two main logic families to choose from when using fastCMOS logic:

ZT 88CT08A/88CT09A CMOS BoardsUse of 80C88 ProcessorThe ZT 88CT09A uses an 80C88 microprocessor instead of the V20used on non-CMOS versions. The 80C88

ZT 88CT08A/88CT09A CMOS BoardsAddition of Optional 8087(-2)As described in Chapter 7, "Numeric Data Processor," a specialmodule is available

ZT 88CT08A/88CT09A CMOS BoardsSlowing down the processor clock is useful for power-criticalapplications that don’t always require full speed processin

ZT 88CT08A/88CT09A CMOS BoardsIf the processor must operate at slow processor speed 100% of thetime, hardware jumper W46A may select this, leaving the

ZT 88CT08A/88CT09A CMOS BoardsThe mechanism used to stop and restart the processor clock is part ofthe 82C85 clock chip, which is supplied only on the

ZT 88CT08A/88CT09A CMOS BoardsELECTRICAL/ENVIRONMENTAL DIFFERENCESIncreased Temperature RangeThe ZT 8808A and ZT 8809A boards are rated for operation

CUSTOMER SUPPORTIf you have a technical question, please call Ziatech’sCustomer Support Service at one of the following numbers.Corporate Headquarters

IntroductionClock Slowdown & Halt Restart (CMOS boards only)For power conservation, the ZT 88CT08A and ZT 88CT09A containtwo features to slow down

ZT 88CT08A/88CT09A CMOS BoardsIf you take advantage of the Clock Slowdown feature, typical powerconsumption is reduced to 132 mA with one 64 Kbyte EPR

Appendix AJUMPER CONFIGURATIONSContents PageOVERVIEW ... A-1JUMPER DESCRIPTIONS...

Jumper ConfigurationsJ4J5W1W2 W3W4ABW5ABW6ABW7ABW8ABW9ABW10ABW11ABW12Figure A–1. W1 - W12 Jumper Block.A-2

Jumper ConfigurationsJUMPER DESCRIPTIONSTable A-1Jumper Descriptions.JUMPER # DESCRIPTIONW1 Install this jumper when using the ACPower-Fail Detect opt

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW2 Jumper W2 ties the power-fail non-maskableinterrupt request (PNMI

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW4(A,B) Installing W4A ties the STD bus pinINTRQ1* (previously RESER

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW6(A,B) Jumper W6A brings the STD bus interruptrequest (INTRQ*), inv

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW8(A,B) Install W8A to bring timer 1 output to theinterrupt request

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW10(A,B) Select jumper W10A to bring the frontplaneinterrupt request

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW11(A,B) Install jumper W11A to bring frontplaneinterrupt request 7

Chapter 2GETTING STARTEDContents PageOVERVIEW ... 2-2UNPACKING...

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW12 Install jumper W12 to bring battery groundreference to the timek

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32ABABW30ABABABW13W14W15W16ZT 8809A REV. AJ6J3J2J1LPTTIMERCOUNTERCOM2COM1Figure A–2. W

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW13(A,B) Jumpers W13 A and B control the enablingand disabling of th

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW13(cont.) Refer to the descriptions of jumpers W16-18and W21 if att

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW14 Jumper W14 controls enabling and disablingof RS-422/485 receiver

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW15(A,B) Install W15A to bring connector J2 pin 13 tothe input of th

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW17(A,B) Install W17A to bring J2 pin 1 to theRS-422/485 driver from

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW14-W19,W21-W22,W29-W32The following table shows jumperassignments f

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32W30W13W14W15W16ZT 8809A REV. AJ6J3J2J1LPTTIMERCOUNTERCOM2COM1Figure A–3. COM2 Config

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32ABABW30W13W14W15W16ZT 8809A REV. AJ6J3J2J1LPTTIMERCOUNTERCOM2COM1Figure A–4. COM2 Co

Getting StartedOVERVIEWThis chapter includes all the information you need to properly installthe ZT 8809A into an STD bus card cage. You should read t

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32W30W13W14W15W16ZT 8809A REV. AJ6J3J2J1BBBBBALPTTIMERCOUNTERCOM2COM1Figure A–5. COM2

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32W30W13W14W15W16ZT 8809A REV. AJ6J3J2J1BBBBBALPTTIMERCOUNTERCOM2COM1Note: Select W13

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW23-W28(DCE †,DTE)These jumpers allow reconfiguration of theRS-232-C

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32W30W13W14W15W16ZT 8809A REV. AJ6J3J2J1BBBBBALPTTIMERCOUNTERCOM2COM1Figure A–7. COM1

Jumper ConfigurationsW17W18W19W20W21W28W27W26W25W24W23W22W29W31W32W30W13W14W15W16ZT 8809A REV. AJ6J3J2J1BBBBBALPTTIMERCOUNTERCOM2COM1Figure A–8. COM1

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW34Install W34 to bring the 1.19318 MHz clock tothe timer 2 clock in

Jumper ConfigurationsW33W46ABABW43ABABABABW39ABW36W35W45W34W44 W40 W38W42W41W68ABFigure A–9. W33-W36, W38-W46, W68 Jumper Blocks.A-26

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW36(A,B)Select W36B to insert one wait state on all CPUcycles. Selec

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW38(A,B) Install jumper W38A to battery back theRAM 3/EPROM 0 socket

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW39 This jumper controls the use of the printerport signal ERROR*. R

Getting StartedWHAT’S IN THE BOX?The items listed below are included in a standard ZT 8809A order.The list does not include options such as system lev

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW40-W42,W43(A,B)Assign these jumpers to configure socket3D1 for the

Jumper ConfigurationsJUMPER PINASSIGNMENTSW43BAW39AW39W40BW45AW44A W41W45BW44B W4216K byte EPROMW4132K byte EPROM64K BYTE EPROM or128K byte EPROMW44A-

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW44-45(A,B),W49(A,B)These three jumpers select the chip sizeto be us

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW46(A,B) Installing W46B allows the printer portsignal Select In* (S

Jumper ConfigurationsW49 W48AW47BABW37W66AW50BCJ7W67Figure A–11. W37, W47-50, W66-W67 Jumper Blocks.A-34

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW47(A,B),W48These jumpers control the interrupt scheme.Install jumpe

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW50(A,B) Install jumper W50A to bring the interruptoutput (INT) from

Jumper ConfigurationsW51W52W53W54W55W56W57W58W59BAW50W66BABAW48W49W47J7Figure A–12. W51 - W59 Jumper Block.A-37

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW51,W52 Install W51 and remove W52 to bring the8087 interrupt output

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW53 Install W53 to enable the ZT 8809A to drivethe STD bus signal DC

Getting StartedSYSTEM REQUIREMENTSPhysical RequirementsThe ZT 8809A is designed to be used in an STD bus system. It istherefore physically and electri

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW54 Remove W54 when installing the optionalzSBC 337 module for use o

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW55-W59 These jumpers control the memory map forsockets 3D1, 5D1, 7D

Jumper ConfigurationsTable A-2Memory Addressing, W55-W59.Memory AddressingMemory Configuration For Each SocketW55 W56 W57 W58 W59 3D1 5D1 7D19D132 KBR

Jumper ConfigurationsTable A-2Memory Addressing, W55-W59 (continued).Memory Addressing (continued)Memory Configuration For Each SocketW55 W56 W57 W58

Jumper ConfigurationsTable A-2Memory Addressing, W55-W59 (continued).Memory Addressing (continued)Memory Configuration For Each SocketW55 W56 W57 W58

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW60 Install W60 to ground the STD bus signalMEMEX. Remove W60 to pul

Jumper ConfigurationsW61 W60W62W63W64ABABW65Figure A–13. W60 - W65 Jumper Block.A-46

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW62 Install W62 to allow the STD bus signalCNTRL* to be driven by th

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW63 Install W63 to connect the STD bus auxiliaryground (AUXGND) sign

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW64(A,B) Install W64A to drive the STD bus writesignal (WR*) during

Getting StartedImportant Note: The ZT 8809A CPU uses an 82C84A or82C84B as the clock generator. The following specialconsiderations should be observed

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW65(A,B) Install W65B to drive the STD bus writesignal (WR*) during

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW66 Removing jumper W66 allows an off-boardserial port to be mapped

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW67 Installing jumper W67 connects the parallelport signal SLIN* to

Jumper ConfigurationsTable A-1Jumper Descriptions (continued).JUMPER # DESCRIPTIONW68(A,B) Memory size selection jumper for socket7D1. The "B&quo

Jumper ConfigurationsZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39W43W

Jumper ConfigurationsZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39W43W

Jumper ConfigurationsZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39W43W

Appendix BSPECIFICATIONSContents PageOVERVIEW ... B-1ELECTRICAL AND ENVIRONMENTAL...

SpecificationsELECTRICAL AND ENVIRONMENTALThe ZT 8809A meets the electrical and environmental parameters ofthe STD-80 Series Bus Specification. These

SpecificationsBattery Backup Characteristics(Vcc < 4.75 V)32 Kbyte Static RAM Data Retention and Real-Time ClockOperation: 1.5 years min., 10 years

Getting StartedEnvironmental RequirementsThe ambient temperature must be maintained at 0˚ to +65˚ Celsius forproper operation and to avoid possible da

SpecificationsTable B-1STD Bus Signal Loading, P Connector.+5 VDCGNDDCPDN*D7/A13 [1]D6/A22 [1]D5/A21 [1]D4/A20 [1]A15A14A13A12A11A10A9A8 R

SpecificationsTable B-2STD Bus Signal Loading, E Connector.LOCK*XA23XA22XA21XA20RSVD+5 VDCDREQx*GNDD31D30D29D28GNDD15D14D13D12D11D10D9D8MASTER16*AENx*

SpecificationsMECHANICALThe ZT 8809A meets the STD-80 Series Bus Specification for allmechanical parameters except component lead length protruding fr

SpecificationsTable B-3Mechanical Specifications.Board Length ... 16.5 cm (6.500 ±0.025 in)Board Width ... 11.4cm(

Specifications4.5003.610.455.5252.16.122.056.500All dimensions in inches..40.230C1C2V208087CPU BOARD.210.690Socketsfor V20zSBC 337Spacer SocketFigure

SpecificationsCONNECTORSThe ZT 8809A has nine connectors to interface to the I/O cables, theSTD bus, the STD 32 bus, and application-specific devices.

SpecificationsJ3 and J4: Connectors J3 and J4 are latching 10-pin (dual 5-pin)male transition connectors with 0.1 inch lead spacing.J3 is used for the

SpecificationsP Connector(Component Side)E Connector(Solder Side)STD 32 STD 32E13 E14P01 P02E15 E16P03 P04E17 E18P05P06E19 E20P07 P08E21 E22P09 P10E23

SpecificationsZT8809A REV AW1J4J3 J2 J1J5J6J7Pin 1Pin 1P1LPTINTERRUPTSTIMERCOUNTERCOM2 COM1Figure B–4. ZT 8809A Connector Locations.B-12

SpecificationsTable B-4J1 Pin Assignments (RS-232-C).Signal Pin Number DescriptionDTE† DCE††TXD 3 5 Transmit DataRXD 5 3 Receive DataRTS 7 9 Request t

Getting StartedINSTALLING THE ZT 8809AThe fastest way to begin using the ZT 8809A is with the addition ofdevelopment software available from Ziatech.

SpecificationsTable B-5J2 Pin Assignments (RS-232-C).Signal Pin Number DescriptionDTE† DCE††TXD 3 5 Transmit DataRXD 5 3 Receive DataRTS 7 9 Request t

SpecificationsTable B-6J2 Pin Assignments (RS-422/485).Signal Pin Number† DescriptionSDA 1 Send Data (negative)SDB 2 Send Data (positive)RDA 14 Receiv

SpecificationsTable B-7J3 Pin Assignments.Signal Pin Number DescriptionOUT0* 1 Counter/Timer 0 OutputGAT0 2 Counter/Timer 0 GateCLK1* 4 Counter/Timer

SpecificationsTable B-8J4 Pin Assignments.Signal Pin Number DescriptionFP1 2 Frontplane Interrupt Level 1FP3 4 Frontplane Interrupt Level 3FP5 6 Front

SpecificationsTable B-10J6 Pin Assignments.Pin IBMSignal Number Equivalent DescriptionPin #PD0 3 2 Parallel Data Bit 0PD1 5 3 Parallel Data Bit 1PD2 7

SpecificationsTable B-11J7 Pin Assignments.Signal Pin Number DescriptionNDPINT 1 Numeric Data ProcessorInterruptNC 2 NoConnectB-19

SpecificationsCABLESTB ANSLEY171-25 25 CONDUCTOR28 GA. STRANDED FLAT CABLE 40" 1"PIN 1BLUE WIRETB ANSLEY 622-25S FEMALE25 PIN "D"

SpecificationsTB ANSLEY171-25 25 CONDUCTOR28 GA. STRANDED FLAT CABLE 40" 1"PIN 1BLUE WIRETB ANSLEY 622-25P MALE25 PIN "D" CONNECT

SpecificationsCON-00052 and CON-00098 Circuit Assembly CA-25DSS-3and Tex-Techs FCH 25A, respectively (screws, if any, removed from backshell)Female 2

SpecificationsTIMINGThe ZT 8809A timing parameters shown in the following pages arebased on the STD bus CLOCK* signal. The CLOCK* signal has riseand f

Getting StartedZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39W43W46W13W

SpecificationsCLOCK*MCSYNC*A0-A15IOEXPMEMEXSTATUS 0*STATUS 1*IORQ*MEMRQ*VALIDVALIDVALIDVALIDTTT/TTtW1tW7tW2tW8tW3tW9123W4tD2tW4tD3tD4tD5tD6tH3tH2tH1tH

SpecificationsCLOCK*MCSYNC*A0-A15IOEXPMEMEXDATARD*VALIDTTT/TT123W4tD2tW4tD3tD9tD10tW5tH4tD1tD7tS1A16-A19VALIDtH9tD8tS2tD12tH8tD11SYMBOL PARAMETERMIN M

SpecificationsCLOCK*MCSYNC*A0-A15IOEXPMEMEXDATAWR*VALIDTTT/TT123W4tD2tW4tD3tD9tD14tH4tD1tS1A16-A19VALIDtH10tW6tH8tD15VALIDtD13tH11SYMBOL PARAMETERMIN

SpecificationsT1T2T3TWT4CLOCK*tW4tD2tD1tS4tH14tS5tH14tH14tS4tS7A0-A19tH14tS5WAITRQ* (2)WAITRQ* (2)MCSYNC*SYMBOLPARAMETERMIN MAX MAX MAX MAXMIN MIN MIN

SpecificationsCLOCK*(1)BUSRQ*DBUSD0-D7tD23tD21CPU USEBUSAK*tD22CPU USEtD24tD25DMA USEA0-A15CPU USECPU USE(2)CONTROLtD27DMA USEDMA USECPU USECPU USEtD2

SpecificationsCLOCK*MCSYNC*(2)DATABUS(3)A0-A15D0-D3UNDETERMINEDVALID CASCADE #FLOATT1tD36tD37tD38tH18tH13tD18T2T3T4T1T2T3T4INTAK*tD19tD18tD19tD9tD20tD

Appendix CCUSTOMER SUPPORTContents PageOVERVIEW ... C-1TROUBLESHOOTING...

Customer SupportTROUBLESHOOTINGPowering Up STD ROMIf you are having difficulty powering up under STD ROM, be sure theEPROM, RAM, jumpers, and cable ar

Customer Support• Some things to check if the system is not working:1. Two ZT 8809A frontplane connectors accept the ZT 90014serial cable. STD ROM wor

Customer SupportPowering Up STD DOSBe sure the ZT 8809A is seated securely into the card cage and thepower switch is off. Plug the card cage into a 12

Getting StartedConfiguring the ZT 8809A for STD ROMThe STD ROM development system is available as an option to theZT 8809A for software development. I

Customer Support• PC-Assisted with a terminal or video board - The PC-Assisted system can also communicate with a terminal viaCOM2 or through a Ziatec

Customer Support• The Automation Engine is available for OEM systemdesigners or high volume users of the ZT 8809A STD DOSsystem. The ZT 8809A is shipp

Customer Support2. If the system completes the RAM test, but does notcontinue, check the following:a) Check the assignment of jumpers W57-W59, asexpla

Customer SupportZT 8808A/8809A REVISION HISTORYThe ZT 8808A/8809A has undergone several revisions, some ofwhich affect the functioning of the board fr

Customer SupportRELIABILITYZiatech has taken extra care in the design of the ZT 8809A to ensurereliability. The four major ways in which reliability i

Customer SupportWARRANTYZiatech Hardware: Within two years of shipping date, Ziatech willrepair or replace products which prove to be defective in mat

Customer SupportTECHNICAL ASSISTANCEYou can reach Ziatech’s Customer Support Service at one of thefollowing numbers.Corporate Headquarters: (805) 541-

Customer SupportRETURNING FOR SERVICEBefore returning any of Ziatech’s products, you must obtain aReturned Material Authorization (RMA) number by call

INDEX-A-access times ... 5-14AC converter... 3-19calibr

IndexZT 8809A ...1-5board dimensions... B-7Borland...

PREFACEThe ZT 8808A and ZT 8809A are single board computers designedprimarily for DOS applications on the STD bus. The combination ofthe 8088-compatib

Getting StartedSTD ROM Cable RequirementsA serial link is required for the STD ROM system between frontplaneconnector J1 and the IBM PC or compatible.

Indexelectrical/environmental differences ...13-8functional differences... 3-29, 13-2halt with r

Indexsimple read ...11-8CPU description... 6-1creating EPR

IndexEnd-of-Interrupt (EOI) commands ...12-31automatic EOI mode... 12-32nonspecific EOI

Index-I-IBM-LPT ...2-16IBM PC compatibility... 1-1, 1-9IBM PC pe

Indexinterrupt on terminal count ... 11-16interrupt request register (IRR)... 12-8inter

IndexLOCATE ... 2-7loop counter (LC)... 6-10-M-MEMEX ..

Index-O-operation control words (OCWs) ... 12-16operation of the interrupt controller...12-24autom

Indexprinter interface (see Centronics printer interface)... 9-1priority resolver (PR)... 12-9proc

Indexsummary (16C452) ...8-18reliability... C-9request to s

Indexserial data outputs (SOUT) ... 8-15serial registers... 8-16baud rate

Getting StartedNote: This configures sockets 3D1 and 5D1 for 64 Kbyte ROMs andsockets 7D1 and 9D1 for 128 Kbyte RAMs. Memory mappinginformation may be

IndexSTD DOS ... 2-7, 3-4, 3-8, 5-3cable requirements... 2-16configuring

Indexzero bits ... 10-8timekeeper register...10-6timing dia

Indexwhat’s in the box ... 2-3write protection... 5-3-Z-zSB

Getting Started• Some things to check if the system is not working:1. Two ZT 8809A frontplane connectors accept the ZT 90014serial cable. STD ROM work

Getting StartedConfiguring the ZT 8809A for STD DOSSTD DOS is an optional MS-DOS operating system available for theZT 8809A V20 processor board. If th

Getting StartedZT8809A REV. AW2 W3W4W5W6W7W8W12W9W10W11W64W65W63W62W60W61W51W52W53W54W55W56W57W58W59W50W66W47W49W48W37W33W34W36W35W38W40W39W43W46W13W

Getting StartedSTD DOS Memory RequirementsThe STD DOS/BIOS software is shipped in one EPROM forinstallation onto the ZT 8809A at socket location 5D1 (

Getting StartedSTD DOS Cable RequirementsIf the STD DOS system is not a Stand Alone (SA) system, a seriallink is required between the ZT 8809A and a t

Getting StartedPowering Up STD DOSBe sure the ZT 8809A is seated securely into the card cage and thepower switch is off. Plug the card cage into your

Getting StartedPC-Assisted with a terminal or video board - The PC-Assistedsystem can also communicate with a terminal via COM2, or through aZiatech v

Getting StartedMEMORY ADDRESSINGFigures 2-3 and 2-4 on pages 2-20 and 2-21 show the memoryaddresses occupied by the ZT 8809A, for both STD DOS andSTD

PrefaceSTD bus compatibility, serial communications, interrupts, directmemory access, power-fail protection, and battery backup.Chapter 4, "Appli

Getting StartedFFFFFhDFFFFhD8000h5FFFFh40000h3FFFFh0h256 Kbyte ROM Drivew/ 256 Kbyte EPROM128 Kbyte ROM Drivew/ 128 Kbyte EPROMOn-Board RAMw/ 128 Kbyt

Getting StartedFFFFFhD8000hD7FFFh40000h3FFFFh0h32 Kbyte RAM Driveand Timekeeper128 Kbytesw/ 64 Kbyte EPROMOn-board RAMw/ 128 Kbyte RAMsNote: Shaded po

Getting StartedI/O ADDRESSINGFigure 2-5 on page 2-23 shows the I/O addresses occupied by theZT 8809A, for both STD DOS and STD ROM systems.I/O accesse

Getting StartedFFFFh0400h03FFh03F8h03F7h0380h037Fh02FFh02F8h0040h0000hSerial Port 1 (COM 1)Printer Port 1 (LPT 1)8259A InterruptControllerNote: Shaded

Getting StartedUPGRADING FROM ZT 8806/8807 SYSTEMSIf you are upgrading your existing STD DOS system fromZT 8806/8807 boards to the ZT 8809A DOS system

Getting StartedThese changes affect the ZT 8844 EGA keyboard controller to theextent that the Revision A board is not compatible with the ZT 8809ADOS

Chapter 3THEORY OF OPERATIONContents PageOVERVIEW ... 3-2RELATIVE MICROPROCESSOR PERFORMANCE...

Theory of OperationOVERVIEWThis chapter describes the following system level issues:• Processor performance compared to the IBM PC/XT• STD bus compat

Theory of OperationRELATIVE MICROPROCESSOR PERFORMANCENorton’s System Information version 4.50 was used to measure theZT 8808A and ZT 8809A processor

Theory of OperationSTD BUS COMPATIBILITYThe ZT 8809A is fully compatible with Revision 2.3 of the STD-80Series Bus Specification. This revision of the

PrefaceChapter 11, "Counter/Timers (8254)," describes the maincomponents of the three programmable 16-bit counter/timersimplemented in an In

Theory of OperationSerial Port 1 (COM1)The programming architecture of both serial ports 1 and 2 is the sameas for the popular WD 8250. The baud rate

Theory of OperationSerial Port 2 (COM2)Serial ports 1 and 2 are identical in features and programming withrespect to RS-232-C communication, with one

Theory of OperationTable 3-2Serial Communications Standards.Parameter RS-232-C RS-423-A RS-422-A RS-485Operation Single-ended Single-ended Differentia

Theory of OperationINTERRUPTSThe ZT 8809A supports both maskable and non-maskable interrupts.This section discusses system level issues related to the

Theory of Operation Timer 0Timer 2IR0IR1IR2IR3IR4IR5IR6IR78087 InterruptINTRQ1*FP1/INTRQ*FP3/COM2*Timer 1COM1*Power Fail/FP5/INTRQ2*FP6/LPT1FP7/Inter

Theory of OperationPolled Interrupts on the STD BusThe PIC can be programmed to supply a unique vector for each ofthese interrupt inputs. This means o

Theory of OperationINTERRUPTSOURCE 1ZT 8808A/ZT 8809AINTRQ*INTAK*INTRQ*INTAK*INTRQ*INTAK*INTERRUPTSOURCE 2INTERRUPTSOURCE NINTRQ*INTAK*STD BUSINTERRUP

Theory of OperationSTD Bus Vectored InterruptsFor more demanding applications, it may be necessary to support eachSTD bus interrupt source with a uniq

Theory of OperationSTD Bus Cascaded InterruptsTo allow for a greater number of interrupts, additional interruptcontrollers may be added to the STD bus

Theory of Operationa unique vector. If STD DOS is installed, this number decreasesdepending upon the number of devices in the system.Non-MaskableInter

CONTENTSI. INTRODUCTIONChapter 1. INTRODUCTION 1-1OVERVIEW... 1-1ZT 88CT08A and ZT 88CT09A...

Theory of OperationDIRECT MEMORY ACCESS (DMA)The ZT 8809A supports Direct Memory Access (DMA) transfersbetween local memory and STD bus system memory

Theory of OperationDMA OperationFigure 3-5 shows the interface between the ZT 8809A and an STDbus DMA controller. The signals shown are required for p

Theory of OperationA0-A19D0-D7BUSRQ*BUSAK*RD*WR*MEMRQ*MCSYNC*STD BUS I/O ORMEMORY WITH DMAZT 8808A/ZT 8809AFigure 3–5. DMA With STD Bus Controller.3-1

Theory of OperationPOWER-FAIL PROTECTIONThe ZT 8809A supports both DC and AC power-fail protection.Advantages of each, as well as operation of both ty

Theory of OperationAC Power-FailAll the logic required to detect AC power failure is present on theZT 8809A except the AC converter. This converter is

Theory of OperationThe advantage of AC power-fail detection is that it provides earlywarning of impending DC power failure. When jumper W1 isinstalled

Theory of OperationTo detect AC power failure, the ZT 8809A may use any AC converterthat provides transformer isolated AC voltage of no more than30 VA

Theory of OperationSystem Battery FailFor systems whose power is generated entirely from a large battery,the AC power-fail detection circuit may be us

Theory of OperationBATTERYThe ZT 8809A contains a socket for an optional 1 Amp-hour 3.9 Vlithium battery. As described above, the real-time clock and

Theory of Operationb) Minimum Data Retention Time:Total Current Drain = Clock + RAM + Buffer= 1uA+50uA+80uA= 111 uABattery Life = 1 AHr x 1 Day x 1---

ContentsPhysical Requirements ... 2-4Power Requirements... 2-4Environmenta

Theory of OperationSTATUS INDICATOR (LED)The ZT 8809A includes an LED near the extractor for generalpurpose use. It is turned on by writing a logical

Theory of OperationRESETThe ZT 8809A is equipped with a System Reset circuit that asserts theSTD bus SYSRESET* signal at any time DC voltage is less t

Theory of OperationCMOS VERSIONS OF THE ZT 8808A/8809AThe ZT 8808A and ZT 8809A processor boards are also available inCMOS versions, ZT 88CT08A and ZT

Theory of OperationClock SlowdownPower consumption for CMOS logic is directly proportional to theswitching speed of the device. The higher the clock f

Theory of OperationHalt with Interrupt RestartTo further decrease power consumption from the Clock Slowdownmode described above, the processor clock m

Chapter 4APPLICATION EXAMPLESContents PageOVERVIEW ... 4-2EXAMPLE 1-A: USING SIMPLE INTERRUPTS...

Application ExamplesOVERVIEWThe following examples show simple uses of some of the morecomplex devices on the ZT 8809A board. Each example is describe

Application ExamplesEXAMPLE 1-A: USING SIMPLE INTERRUPTSObjectives• Write a software routine that initializes the 8259A InterruptController on board.•

Application ExamplesSoftware OutlineINITPIC RoutineBEGINInitialize the Interrupt ControllerSend ICW1 - Edge triggered, Single, ICW4 neededSend ICW2 -

Application ExamplesLED_STROBE routineBEGINCheck state of LEDSet it to the opposite stateSend End of Interrupt (EOI) byte to PICReturn from ISRENDINIT

ContentsChapter 4. APPLICATION EXAMPLES 4-1OVERVIEW... 4-2EXAMPLE 1-A: USING SIMPLE INTERRUPTS...

Application ExamplesProgram Code;;**********************************************************;* *;* PROGRAMMING ABSTRACT *;* *;************************

Application Examples;;***********************************************************;* *;* SYSTEM EQUATES *;* *;*****************************************

Application Examples;;***********************************************************;* *;* MACRO DEFINITIONS *;* *;**************************************

Application Examples;***********************************************************;* *;* STACK SEGMENT *;* *;*******************************************

Application Examples;***********************************************************;* *;* INTERRUPT HANDLERS *;* *;**************************************

Application Examples;***********************************************************;* *;* PROCEDURES *;* *;**********************************************

Application Examples;***********************************************************;* *;* TEST CODE *;* *;***********************************************

Application ExamplesEXAMPLE 1-B: HANDLING SLAVE INTERRUPTSObjectives• Write a software routine that initializes the 8259A InterruptController on-board

Application ExamplesSystem ConfigurationThe following example assumes that a ZT 8809A and a ZT 8840 arepresent in the STD bus card cage. All jumpers a

Application ExamplesInitialize the 8840 Interrupt ControllerSend ICW1 - Edge triggered, Cascade, ICW4 neededSend ICW2 - Vector addresses 248 - 255 DSe