Ziatech Corporation ZT 89CT04 Bedienungsanleitung

ZT 89CT04Single Board 386 EX ComputerZT 8904ZT 8903Hardware User Manual

1. Introduction10FEATURES• STD 32 compatible• STD 32 multiprocessing option (not supported by ZT 8903)• 25 MHz Intel® 386 EX CPU• Numeric data pro

12. Watchdog Timer100Stage 1(386EX)System Register 0(7Bh, Bit 1)Stage 1Latch1236ASTB8MHzW11CPUNMIPOR = 1 = RST'I'RQRST1611100 Ms Minimum400

12. Watchdog Timer101Watchdog Timer Clear RegisterThe Watchdog Timer Clear register is programmed with a lockout sequence to enablewatchdog timer mode

12. Watchdog Timer102Watchdog Timer Counter RegistersThe Watchdog Timer Counter registers hold the current value of the down counter.Application softw

12. Watchdog Timer103Watchdog Timer Reload RegistersThe Watchdog Timer Reload registers are programmed with two word operations to setthe reload value

10413. LOCAL BUS VIDEOThe ZT 8904 includes a local bus interface to permit high speed peripherals directaccess to the CPU bus. This bus operates synch

10514. NUMERIC DATA PROCESSORThe ZT 8904 includes a socket at location U26 designed to accept an 80387 numericdata processor. The numeric data process

10615. PROGRAMMABLE LEDThe ZT 8904 includes two Light-Emitting Diodes (LEDs) located immediately below theboard extractor. The green LED is for the op

15. Programmable LED107;-------------------------------------------------------------; led_off turns off the led.;------------------------------------

10816. AC POWER FAILThe ZT 8904 supports AC power-fail detection as a means for giving the applicationadvanced warning of an impending power failure.

109A. JUMPER CONFIGURATIONSThe ZT 8904 includes several options that tailor the operation of the board torequirements of specific applications. Option

1. Introduction11DEVELOPMENT CONSIDERATIONSZiatech offers a variety of software options for ZT 8904 applications. These optionsinclude STD ROM, STAR B

A. Jumper Configurations110W1W2W3W4W5W6W7W8W9W10W11W12W13W14W15W16W17W18W19W20W21W22W23W24W25W26W27W28W29W30W31abZT 8904DOS Factory Default Configurat

A. Jumper Configurations111Jumper DescriptionsThe following topics list the jumpers in numerical order and provide a detaileddescription of each jumpe

A. Jumper Configurations112W12-15RS-485 Duplex Selection - independently selects half duplex or full duplex for each RS-485 channel. The COM1 and COM2

A. Jumper Configurations113W17-22Maskable Interrupts - assigns up to nine interrupt sources to the interrupt controllerinputs. Each interrupt input ha

A. Jumper Configurations114W24-27CPU Configuration - connects external hardware functions to multiplexed CPU pins.The CPU multiplexes DMA channel 0 an

A. Jumper Configurations115W28-31RS-485 Transmitter Configuration - independently configures the transmitter inputsource and transmitter enable for th

116B. SPECIFICATIONSThis appendix describes the electrical, environmental, and mechanical specifications ofthe ZT 8904. It also includes illustrations

B. Specifications117Battery Backup CharacteristicsBattery Voltage: 3 VBattery Capacity: 255 mAHReal-time clock requirements: 5 µA maximum (when Vcc is

B. Specifications118STD Bus Signal Loading, P Connector+5 VDCGNDDCPDN*PIN (CIRCUIT SIDE)OUTPUT DRIVEINPUT LOADMNEMONICD7/A13 [1]D6/A22 [1]D5/A21

B. Specifications119STD Bus Signal Loading, E ConnectorPIN (CIRCUIT SIDE)INPUT LOADMNEMONICOUTPUT DRIVELOCK*XA23XA22XA21XA20RSVD+5 VDCDREQx*GNDD31D30D

1. Introduction12386 EX CPUThe ZT 8904 supports the Intel 386 EX CPU operating at 25 MHz. The 386 EX is a fullystatic 32-bit CPU core integrated with

B. Specifications120MECHANICAL SPECIFICATIONSThe following topics list mechanical specifications, including card dimensions andweight, connectors, and

B. Specifications121ConnectorsThe ZT 8904 includes 9 connectors to interface to the STD bus and application specificdevices. Connector positions are i

B. Specifications122Viking S3VT68/5DE12 or equivalent for the card extender. The figure below,"P/E Connector Pinout," shows pin assignments

B. Specifications123Connector DescriptionsConnector FunctionJ1 PeripheralJ2 Frontplane InterruptJ3 AC Power FailJ4 Parallel I/OJ5 Memory ExpansionJ6 L

B. Specifications124J1 Peripheral Pinout (continued)Pin Signal Type Description Pin Signal Type Description13 COM3 RXD In Receive Data 53 PD2 In/Out D

B. Specifications125J2 (Frontplane Interrupt)J2 is a latching 10-pin (dual 5-pin) male transition connector with 0.1 inch contactspacing. Frontplane i

B. Specifications126J3 (AC Power Fail)J3 is a latching 2-pin male low-profile header with 0.1 inch contact spacing. The ACinput signals for the option

B. Specifications127J4 (Parallel I/O)J4 is a 50-pin (dual 25-pin) vertical male header with 0.1 inch contact spacing. The 24general purpose parallel I

B. Specifications128J5 (Memory Expansion)J5 is a 54-pin (dual 27-pin) socket with 0.1 inch contact spacing. J5 includes memoryaddress, data, and contr

B. Specifications129J6 (Local Bus)J6 is a 100-pin (dual 50-pin) vertical receptacle with 0.05 inch contact spacing. Thisconnector includes the signals

1. Introduction13Memory and I/O AddressingThe ZT 8904 includes 1 Mbyte of system RAM, 1, 2, or 4 Mbytes of Flash, and128 Kbytes of battery-backed RAM.

B. Specifications130J6 Local Bus Pinout (continued)Pin# Signal Type Description Pin# Signal Type Description24 A19 Out CPU Address 74 GND ------ Groun

B. Specifications131J7 (Auxiliary Power)J7 is a location for a 2-pin latching COMBICON connector with 0.2 inch contact spacing.J7 includes the power a

B. Specifications132J8 (Optional IDE)J8 is an optional 44-pin (dual 22-pin) vertical receptacle with 2 mm contact spacing. AnIDE interface is provided

B. Specifications133J9 (Reserved)J9 is reserved for Ziatech test purposes.CablesThe following cables are available from Ziatech Corporation. They are

B. Specifications134MALESFEMALES11"9.5"P1 - COM 4P1 - COM 2P1 - COM 3 P1 - COM 1P1 - J2 P1 - LPTP1 - J12 - 61 - 13 - 24 - 75 - 36 - 87 - 48

B. Specifications1351 - 45 - 14P2J11 1/2"HEAT SHRINK TUBING 1/16" DIAMETERBLACK ALPHA FIT 221-1/16SINGATRONDJ-002-B5P DIN CONNECTORP2 DETA

B. Specifications136 HIRSCHMANN #MAK 50 S (930172-517) FEMALE 5 PINS AT 180 DIN CONNECTOR678910115214313412511PIN ASSIGNMENT CHARTP2RIBBON CABLEWIR

B. Specifications137P1 - KEYBOARD CONN.P112345SHIELD24-313PIN ASSIGNMENT CHARTRIBBON CABLEWIRE #678910115214313412511P2 DETAILAMP 207467-1SHELLAMP P/

B. Specifications138MALESFEMALES11"9.5"408011"P1COM 2COM 1J1LPT40116159659Justify 6 Conductors to Pin 116591141325P1 - COM 2 P1 - COM 1

139C. PIA SYSTEM SETUP CONSIDERATIONSThe 16C50A Parallel Interface Adapter (PIA) device used on the ZT 8904 is designedby Ziatech to offer bidirection

1. Introduction14The serial ports are configured as DTE and are available through the J1 80-pinfrontplane connector. Optional cables convert the seria

C. PIA System Setup Considerations140Power Supply Sequence MismatchA common application is to interface to a 24-position ZT 2226, Opto 22, or equivale

C. PIA System Setup Considerations141One solution is to switch the external signals' power supply with an output that iscontrolled by the compute

C. PIA System Setup Considerations142Signal Level MismatchPower supplying the external signal in Figure 1 is always relative to the PIA inputcircuitry

C. PIA System Setup Considerations143PowerSupply16C50APIAZT 8904Interface CableExternalPowerSupply24-PositionorCustomApplicationVcc24Figure 7. Compute

C. PIA System Setup Considerations144Typically, optical isolators are used to help remove electrical noise while providing fordifferent grounds. Separ

C. PIA System Setup Considerations145them to conduct and allowing the majority of energy to flow through them instead ofthrough the diode clamps. The

146D. CUSTOMER SUPPORTThis appendix offers technical assistance and warranty information for this product, andalso the necessary information should yo

D. Customer Support147Once you have an RMA number, follow these steps to return your product to Ziatech:1. Contact Ziatech for pricing if the warrant

D. Customer Support148TRADEMARKSAT® is a registered trademark of IBM.Intel® and Intel386® are registered trademarks of Intel Corporation.Motorola® is

1050 Southwood DriveSan Luis Obispo, CA 93401 USATel: (805) 541-0488FAX: (805) 541-5088E-Mail: [email protected]: http://www.ziatech.co

1. Introduction15TimersThree timers are included on the ZT 8904. Operating modes supported by the timersinclude interrupt on count, frequency divider,

1. Introduction16Keyboard ControllerThe ZT 8904 includes a PC/AT® keyboard controller that operates when the zVID localbus video adapter is installed.

172. GETTING STARTEDThis chapter summarizes the information needed to make the ZT 8904 operational.Read this chapter before attempting to use the boar

2. Getting Started18• Local RAM Drive - 8-bit battery-backed RAM (not available on the ZT 8903) pagedfor 128 Kbytes• System BIOS - 16-bit pseudo sta

2. Getting Started19180000h-3FFFFFh140000h-17FFFFh100000h-13FFFFh080000h-0FFFFFh050000h-07FFFFh010000h-04FFFFh00E000h-00FFFFh00D000h-00DFFFh00C800h-00

2CONTENTSMANUAL ORGANIZATION...61. I

2. Getting Started20F900h-FFFFhF800h-F8FFhF500h-F7FFhF4D0h-F4FFhF4C0h-F4CFhF400h-F4BFhF100h-F3FFhF000h-F0FFh03F8h-03FFh03F6h-03F7h02E8h-02EFh02F8h-02F

2. Getting Started21J3J2J1J4J6J5J2 (FRONTPLANE INTERRUPT)J3 (AC POWER FAIL)J5 (MEMORY EXPANSION)J6 (LOCAL BUS)J4 (PARALLEL I/O)J1 (SERIAL/PRINTE

2. Getting Started22The ZT 8904 is configured during the boot sequence by the BIOS. The BIOS usessystem configuration information stored

233. STD BUS INTERFACEThe ZT 8904 includes several I/O devices common to industrial control applications.The ZT 8904 also operates with the STD 32 bus

3. STD Bus Interface24STD 32 BUS COMPATIBILITYThe ZT 8904 is compatible with Revision 1.2 of the STD 32 Bus Specification (Ziatechpart number ZT MSTD3

3. STD Bus Interface25Maskable InterruptsThe STD bus maskable interrupts monitored by the ZT 8904 are INTRQ* (P44),INTRQ1* (P37), INTRQ2* (P50), INTRQ

3. STD Bus Interface26In an edge-triggered architecture, multiple interrupt sources should not share the sameinterrupt request signal because it is po

3. STD Bus Interface27RESETThe ZT 8904 is automatically reset with a precision voltage monitoring circuit thatdetects when Vcc is below the

3. STD Bus Interface28I/O SLAVEMEMORY SLAVEZT 8904TEMPORARYMASTERZT 8904TEMPORARYMASTERZT 8904TEMPORARYMASTERZT 8904PERMANENTMASTERSLOT XARBITERTMZT20

3. STD Bus Interface29I/O SLAVEMEMORY SLAVEZT 8832INTELLIGENTI/OZT 8832INTELLIGENTI/OZT 8832INTELLIGENTI/OZT 8832INTELLIGENTI/OZT 8904TMZT200EmbeddedC

Contents34. INTERRUPT CONTROLLER...31PROGRAM

3. STD Bus Interface30• An STD 32 backplane is required. The STD-80 backplane does not support the busexchange protocol (DREQx* and DAKx*).• A ZT 89

314. INTERRUPT CONTROLLERThe ZT 8904 includes two Intel-compatible 8259 cascaded interrupt controllers thatprovide a programmable interface between in

4. Interrupt Controller32following table. The base address of the master interrupt controller is 20h and the baseaddress of the slave interrupt contro

4. Interrupt Controller33WATCHDOG STAGE 1IR15IDE CONTROLLERSTD BUS INTRQ3*MATH COPROCESSORSERIAL PORT COM3DMA CONTROLLERTIMER/COUNTER 2TIMER/COUNTER 1

4. Interrupt Controller34Interrupt Architecture Initialization Registers (ICW1-ICW4)Each interrupt controller must be initialized before it is used. I

4. Interrupt Controller3576543 210Register: ICW2Address: Base+1Vector Pointer0Access: WriteVectorUpper 5 bits of pointer00Initialization Register ICW2

4. Interrupt Controller36Operational Registers (OCW1-OCW3)The operation of each interrupt controller is managed by three 8-bit operationalregisters. T

4. Interrupt Controller37SLCTSMM76543 2 10Register: OCW3Address: Base + 0Read RegisterAccess: Write00 Do not use0101 Do not use10 Select IR regis

4. Interrupt Controller38Active076543 210Register: IPRAddress: Base + 0Highest Active RequestAccess: Read000 IR000001 IR1010 IR2011 IR3100 IR410

395. COUNTER/TIMERSThe ZT 8904 includes one Intel-compatible 8254 device with a total of threeprogrammable counter/timers. The counter/timers are usef

Contents4PROGRAMMABLE REGISTERS...78BAUD RATE DIVISORS ...

5. Counter/Timers40The six programmable operating modes are summarized in the "Counter/TimerOperating Modes" table following.Counter/Timer O

5. Counter/Timers41PROGRAMMABLE REGISTERSThe counter/timers are accessed through four I/O addresses as shown in the followingtable. Each counter/timer

5. Counter/Timers42Status RegisterEach counter/timer has a Status register. The Status register must be read using themultiple latch command specified

5. Counter/Timers43Control RegisterThe Control register is used to initialize the counter/timers and to select the method ofreading the count and stat

5. Counter/Timers4476543 210Register: Multiple Latch ControlAddress: 43hCounter Selection0Access: WriteCTL001 Counter 01CT1010 Counter 1Status La

456. DMA CONTROLLERThe DMA controller used on the ZT 8904 is contained within the 386 EXmicroprocessor. It improves system operation by allowing exter

6. DMA Controller46connections internal to the 386 EX. Note that the synchronous serial channel is notimplemented on the ZT 8904 in favor of providing

6. DMA Controller47DMA IMPLEMENTATIONThe ZT 8904 DMA architecture external to the 386 EX is illustrated in the followingfigure, "DMA

6. DMA Controller48BUSRQ*/ BRQ_DST/ LPT_DAKLPT_DRQ/ BUSAKEOP12U43ICPSMCI-7S32F4163U18C4ICPSMCI-74FCT540QU18B17ICPSMCI-74FCT540QVCCR8421RESSM-04751VCCR

6. DMA Controller49An external device or an internal peripheral requests service by activating a channel’srequest input (DRQn). A requester in memory

Contents5CONNECTOR DESCRIPTIONS ...123CABLES...

6. DMA Controller50386 EX DMA CONTROLLER REGISTERSThe "386 EX DMA Controller Registers" table below lists the registers associated withthe D

6. DMA Controller51DMA0TAR3 0F086h --- Channel 0 target address 24-25DMA1TAR0 0F002h 0002h Channel 1 target address 0-7DMA1TAR1 0F002h 0002h Channel 1

6. DMA Controller52REGISTER:EXP ADDRESS:AT ADDRESS:ACCESS:00000000D7 D6 D5D4D3 D2D1D0PINCFG0F826h---R/WReservedMust be written with a 0Must be written

6. DMA Controller53Peripheral Connections and MaskThe DMACFG register is used to select of the hardware DRQ sources for each channeland to mask the /D

6. DMA Controller54REGISTER:EXP ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0---0F010hND ND NDND NDND ND NDDMA0REQ1R/W, BP = 1Channel 0 requestor addr

6. DMA Controller55Channel 1 Requestor Address RegistersREGISTER:EXP ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0---R/W, BP = 0Channel 1 requestor ad

6. DMA Controller56REGISTER:EXP ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0---R/W, BP = 0Channel 1 requestor address bit 16Channel 1 requestor addre

6. DMA Controller57REGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0DMA0TAR10F000hR/W, BP = 1Channel 0 target address bit 8Channel 0 target addre

6. DMA Controller58Channel 1 Target Address RegistersREGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0DMA1TAR00F002hR/W, BP = 0Channel 1 target a

6. DMA Controller59REGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0DMA1TAR20F083hR/WChannel 1 target address bit 16Channel 1 target address bit

6MANUAL ORGANIZATIONThe ZT 8904 family of products includes the ZT 8904, ZT 89CT04, and ZT 8903products. The ZT 8904 is a highly integrated 386 EX sin

6. DMA Controller60REGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0DMA0BYC10F001hR/W, BP = 1Channel 0 byte count bit 8Channel 0 byte count bit 9

6. DMA Controller61Channel 1 Byte Count RegistersREGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0DMA1BYC00F0023R/W, BP = 0Channel 1 byte count b

6. DMA Controller62REGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0DMA1BYC20F099hR/WChannel 1 byte count bit 16Channel 1 byte count bit 17Channe

6. DMA Controller63DMA Command RegistersThe DMACMD1 resister is used to enable both channels and to select the rotatingmethod for changing the bus pri

6. DMA Controller64DMA Mode RegistersThe DMAMOD 1 register is used to select a particular channel's data-transfer mode andtransfer direction, and

6. DMA Controller65REGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0---0F01Bh00000000DMAMOD2W/O, D0 specifies channel1= Bits D7-D2 affect channel

6. DMA Controller66DMA Single Channel Mask RegisterUse the DMAMSK register to enable or disable hardware requests for one channel at atime.REGISTER:AD

6. DMA Controller67REGISTER:ADDRESS:AT ADDRESS:ACCESS:D7 D6 D5D4D3 D2D1D0---W/O, D0 specifies channel1= Bits D6 and D4 affect channel 10= Bits D6 and

6. DMA Controller68DMA Interrupt Enable RegisterThe DMAIEN register is used to individually connect channel 0 and channel 1’s transfercomplete signal

6. DMA Controller69DMA Overflow Enable RegisterUse DMAOVFE to specify whether all 26 bits or only the lower 16 bits of the target andrequestor address

Manual Organization7Chapter 11, "System Registers", discusses the three system registers used to controland monitor a variety of functions o

707. REAL-TIME CLOCKThe ZT 8904 includes one Motorola®-compatible 146818 real-time clock. The real-timeclock provides clock and 100-year calendar info

7. Real-Time Clock71Real-Time Clock Register AddressingAddressOffsetFunction Range0h Time-Seconds 0-591h Alarm-Seconds 0-592h Time-Minutes 0-593h Alar

7. Real-Time Clock72Register AInterrupt Rate0765432 10Register: AAddress: Offset+0AhRate SelectionAccess: Read and Write 0000 No Interrupts01UIP000

7. Real-Time Clock73Register BRegister: BAddress: Offset+0BhAccess: Read and WriteSETPIE AIEUIE 0DM24/12DSE76543210Daylight Savings0 Disabled1 Ena

7. Real-Time Clock74Register DRegister: DAddress: Offset+0Dh Access: ReadVRT 076543210000000Valid RAM0 Invalid1 ValidRegister DADDITIONAL INFOR

758. SERIAL CONTROLLERThis chapter discusses operation of the four ZT 8904 serial ports. It providesdescriptions of the two software-configurable seri

8. Serial Controller76Address MappingThe address mapping for the PC standard architecture and the ZT 8904 is shownbelow.Serial Channel PC Port Address

8. Serial Controller77RS-485 OperationTwo of the serial channels, COM1 and COM2, are software programmable for RS-232or RS-485 operation. The RS-485 f

8. Serial Controller78PROGRAMMABLE REGISTERSSix registers are available for initializing and controlling each serial channel. Thefollowing table "

8. Serial Controller79Baud Rate DivisorsBaudRateDivisor(dec/hex)PercentError50 2304/1440h 075 1536/960h 0150 768/480h 0300 384/240h 0600 192/120h 0120

81. INTRODUCTIONThis chapter provides a brief introduction to the ZT 8904. It includes a product definition,a list of product features, a functional b

8. Serial Controller80Register: Divisor Latch MSBAddress: 3F9h DIV=1Access: Read and WriteD15 D14D13 D12D11 D10 D9D876 54321 0Divisor Latch

8. Serial Controller81Interrupt Status RegisterSource076543210Register: Interrupt StatusAddress: 3FAhInterruptAccess: Read0 Active000 INT1 Ina

8. Serial Controller82Line Control RegisterLength76543 210Register: Line ControlAddress: 3FBhCharacter LengthAccess: Read and Write00 5 bitsDIV

8. Serial Controller83Line Status RegisterRegister: Line StatusAddress: 3FDhAccess: Read0 TRBTHRBRKFRMPTY OVRRBR765 4 3 210Receive Buffer0 Empty1

8. Serial Controller84Modem Status RegisterRegister: Modem StatusAddress: 3FEhAccess: ReadDCDRINDSRCTS DDD RITDDRDCS76 5 432 10Delta Clear To Send

859. CENTRONICS PRINTER INTERFACEThe bidirectional printer interface fully supports a Centronics-compatible printer. TheCentronics interface is availa

9. Centronics Printer Interface86Line Printer Control Register7 6 54 3 210Register: Line Printer ControlAddress: 37AhAccess: Read and WriteData Strobe

8710. PARALLEL I/OThe ZT 8904 includes six 8-bit parallel ports for a total of 48 I/O signals. Three of theparallel ports are available to the applica

10. Parallel I/O88Internal Data BusConnector J4DebounceLogicOutputData LatchOutputBufferPassive TerminationInputBufferEventDetectLogicParallel Port Fu

10. Parallel I/O89Input BufferThe input buffer is enabled during read operations to transfer the data from connectorJ4 to the internal data bus. If th

1. Introduction9ZT 8904The ZT 8904 is a highly integrated 386 EX single board computer. The board meets theneeds of a wide range of industrial control

10. Parallel I/O9016C50A Enhanced Operating ModeEnhanced operation adds extended event sense and input debounce capabilities. It isselected with four

10. Parallel I/O91Enhanced Bank 2 I/O Port AddressingAddress Register Read Operation Write Operation0078h Debounce Configure Status Control0079h Debou

10. Parallel I/O9276543210BankBank10000Port Port Port210Port Write Inhibit0 Inactive1 ActiveBank Address00 Bank 001 Bank 110 Bank 211 UndefinedRegiste

10. Parallel I/O937 6543 210Register: Event Sense Manage (Read)Mode: Enhanced (Bank 1)Address: 7EhAccess: Read and WriteEvent Interrupt0 Inactive1 Act

10. Parallel I/O947654321000000Port Port Port21 0Debounce0 Disable†1 EnableRegister: Debounce ConfigureMode: Enhanced (Bank 2)Address: 78hAccess: Rea

10. Parallel I/O957654321000 0210Port Write Inhibit0 Inactive1 ActivePortPortPortMode: Enhanced (Bank 0)Address: 7FhAccess: Read and WriteRegister: Ma

9611. SYSTEM REGISTERSThree system registers are used to control and monitor a variety of functions on theZT 8904. These registers are implemented wit

11. System Registers9776543210System Register 1LSI LSORVORVIWDTSTD PFLPRMPermanent Master Operation0 Temporary1 PermanentPower Fail NMI0 Active1 Inact

11. System Registers9876543210System Register 2LED BDS VPP VMX C2S C1S KBD MIRMultiprocessing Interrupt0 Active1 InactiveKeyboard Interrupt0 Local1 Sy

9912. WATCHDOG TIMERThe primary function of the watchdog timer is to monitor ZT 8904 operation and takecorrective action if the system fails to functi